Conventional or bulk semiconductor transistors are formed in a semiconductor substrate by implanting a well of either P-type or N-type conductivity silicon in a silicon substrate wafer of the opposite conductivity. A field oxide layer functions to prevent surface inversion. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). Each of these FETs must be electrically isolated from the others in order to avoid shorting the circuits. These FET's are typically interconnected through metal layers above the bulk substrate to form logic circuits. Typically, the interconnections will be structured to interconnect both P-Channel and N-Channel FET's in accordance with known complimentary metal oxide semiconductor (CMOS) techniques to minimize power consumption.
A problem with bulk semiconductor logic circuits is that a relatively large amount of surface area is needed for the electrical isolation of the various FETs which is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate slows the speed at which a device using such transistors can operate.
In order to deal with the junction capacitance problem and reduce size, silicon on insulator technology (SOI) has been gaining popularity. One method of forming an SOI wafer includes using conventional oxygen implantation techniques to create an insulating buried oxide layer at a predetermined depth below the surface of a bulk wafer. The implanted oxygen oxidizes the silicon into insulating silicon dioxide in a guassian distribution pattern centered at the predetermined depth to form the insulating buried oxide layer. A second method of forming an SOI wafer includes depositing an insulating layer of silicon dioxide on the surface of a first wafer and then bonding such wafer to a second wafer using a heat fusion process.
Utilizing SOI technology, an SOI FET includes a source region and drain region of a first semiconductor type on opposing sides of a channel region of the opposite semiconductor type. An SOI FET is isolated by etching a trench around the periphery of an island in the thin semiconductor layer above the insulating buried oxide layer in the SOI wafer. Appropriate portions of the island are then doped to form the source region, drain region, and channel region. It is recognized in the art that an SOI FET will occupy less surface area on the substrate and, because it is isolated from the silicon substrate by the insulating trench and the insulating buried oxide layer, will have a lower junction capacitance than an equivalent bulk semiconductor FET. This provides for the ability to put larger logic circuits in less space and operate such circuits with reduced power consumption.
However, the power consumption at which an SOI FET can operate is still limited by the dimension between the channel/source junction and the channel/drain junction. While it is recognized that a narrower channel region will provide for reduced power consumption, known SOI fabrication techniques have a limited resolution resulting in a minimum island size.
Accordingly, there is a strong need in the art for an SOI circuit structure, and a method for forming such structure, that includes an SOI FET structure that provides for reduced channel width and reduced FET capacitance to provide for reduced power consumption operation.